Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device capable of employing a max power down mode.
Generally, semiconductor devices, e.g., Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), include a mode register set inside. The semiconductor devices perform diverse operations based on the value set in the mode register set. The value of the mode register set is set to a desired value in response to a signal inputted through a plurality of address pins. Here, the operation of setting a value in the mode register set may be defined by external command signals.
The external command signals include a chip selection signal, a row address strobe signal, a column address strobe signal, and a write enable signal. A semiconductor device performs not only the setting operation of the mode register set but also a read operation, a write operation, and a pre-charge operation based on a combination of the external command signals.
Meanwhile, semiconductor devices are being developed toward low-power operation according to the market demands. In an effort to achieve the low-power operation, semiconductor devices are supported in a max power down mode. Max power down mode is an operation mode for minimizing power consumption and it may be defined in specifications for the semiconductor device.
FIG. 1 is a timing diagram illustrating a conventional operation in a max power down mode. Herein, ‘NOP’ denotes that external command signals CMD and a chip selection signal CSB have values which are not relevant to the operation of a semiconductor device. ‘MRS’ denotes that the external command signals CMD and the chip selection signal CSB have values for setting the mode register set. ‘VALID’ denotes that the external command signals CMD and the chip selection signal CSB have values corresponding to a certain operation of a semiconductor device other than the setting operation. Here, the external command signals CMD may be the row address strobe signal, the column address strobe signal, and the write enable signal except the chip selection signal CSB.
Hereafter, an operation of entering the max power down mode and an operation of exiting the max power down mode are described with reference to FIG. 1.
First, during the setting operation of the mode register set defined in response to the external command signals CMD and the chip selection signal CSB, when the mode register set is set to indicate a max power down mode in response to an external address signal, the semiconductor device enters the max power down mode MPD_NTR.
In other words, when the chip selection signal CSB is enabled to a logic low level, the mode register set performs the setting operation based on the external command signals CMD. At the setting operation, the mode register set may be set to indicate the max power down mode in response to the external address signal.
Here, the mode register set outputs a control signal corresponding to the operation of entering the max power down mode, and a buffer unit which receives the external command signals CMD and the external address signal is disabled in response to the control signal. Therefore, the semiconductor device does not perform a buffering operation according to the external command signals CMD and the external address signal and reduces power consumption.
Meanwhile, the semiconductor device uses the chip selection signal CSB and a clock enable signal CKE to exit the max power down mode. In other words, when the chip selection signal CSB is enabled to a logic low level and the clock enable signal CKE transitions from a logic low level to a logic high level, the semiconductor device exits the max power down mode MPD_EXT.
To be specific, the semiconductor device sets the mode register set to have a value corresponding to the max power down mode in response to the external command signals CMD, the chip selection signal CSB, and the external address signal, and performs an operation of entering the max power down mode based on a control signal generated from the set mode register set. Subsequently, in response to the chip selection signal CSB and the clock enable signal CKE, the semiconductor device performs an operation of exiting the max power down mode.
Therefore, the semiconductor device is to keep a buffer element for the chip selection signal CSB and the clock enable signal CKE in the enabled state in order to exit the max power down mode. In addition, the semiconductor device receives a reset signal for controlling a reset operation of a circuit such as the mode register set, and a buffer element which receives the reset signal is to be kept in the enabled state even during the max power down mode.
After all, when the conventional semiconductor device enters the max power down mode, the buffer element for receiving the chip selection signal CSB, the clock enable signal CKE, and the reset signal are to be kept in the enabled state all the time. Therefore, the semiconductor device consumes power for at least three buffer elements although it enters the max power down mode.